STARC selects Asygn's Tactyle as the AMS System Level Design & Verification solution for STARCAD-AMS design flow

March 13, 2013 - Asygn, (www.asygn.com) a company specialising in Mixed-Signal IC System Design, today announced that STARC, the Japanese electronic design consortium, has selected Asygn's Tactyle as the AMS System Level Design & Verification solution for the Japanese semiconductor industry's next-generation STARCAD-AMS Analog/Mixed Signal reference flow.

STARC (The Semiconductor Technology Academic Research Center) is a consortium founded in 1995 by leading Japanese semiconductor companies. STARC's mission is to contribute to the growth of the Japanese semiconductor industry by developing leading-edge SoC design technologies.

"The STARCAD-AMS flow initiative aims to reduce the turnaround time (TAT) for mixed-signal design by half for STARC member companies," said Kunihiko Tsuboi, Senior Manager of STARC's R & D Department-2. "It is well-known that early design decisions have a huge impact on (1) final product cost, (2) design productivity later in the flow. Further, the analog behavior of a mixed-signal system can be very hard to verify through simulation because of the sheer size and complexity of modern AMS designs. The increased use of embedded digital control and compensation circuitry in AMS, as well as issues associated with analog on the latest technology nodes, exacerbate these problems. It is therefore critical that modern AMS systems are carefully, and quantitatively architected from the start, and that the system-level view is accessible late in the design flow in order to verify macroscopic analog behavior."

"When considering our TAT reduction goals, we realised that a strong system-level AMS simulation tool would be essential. Extensive evaluation work with Asygn's Tactyle has convinced us that this tool can fit smoothly into the STARCAD-AMS flow and produce very significant productivity improvements.", said Nobutaka Okumura, Researcher of the Mixed Signal Design Technology Group. "We particularly appreciate Tactyle's ability to integrate with our existing toolset (schematic capture and other types of simulator), its easy-to-use modeling approach (based on schematic capture), its ability to align with transistor-level and other types of model, and its extremely high simulation speed. The very fast turnaround from modifying design parameters to receiving new response curves makes it easy to explore architectural possibilities. In many simulation scenarios, runtimes can be so fast as to make parameter tuning an interactive process, and the tool has a plotter that actually allows you to see response curves update as parameters are controlled from the mouse. This feature alone is a great help in understanding circuit sensitivities and in testing one's intuition for a circuit's behavior."

"We are very pleased that Tactyle has been certified and selected by STARC based on a set of strict criteria". Said Daniel Saias, President of Asygn SAS. "We look forward to working with STARC and member companies in deploying Tactyle for system level AMS architecture development and post-implementation verification."

About Asygn
Asygn is a Grenoble-based startup, specialising in the design and verification of analog/mixed-signal and RF systems, and in software for performing these tasks. Its expertise in high-speed, analog system level simulation has allowed it to develop specialised simulators for imaging applications. The technology is used throughout the design flow, from architecture definition through design signoff to silicon debug. The company has also had notable successes in the areas of mobile phone radios; MEMs and NEMs sensors; digital and fractional PLLs; high speed IOs. The company is based in Montbonnot, close to Grenoble, France. For more information, please visit www.asygn.com.